Sliding interval event detector

ABSTRACT

A system for detecting the occurrence of a predetermined number of pulses in a predetermined &#39;&#39;&#39;&#39;sliding&#39;&#39;&#39;&#39; test time interval. A plurality of timers is provided each having a timing interval equal to the test time interval. Each input pulse sets one of the timers. To detect N pulses in the test time interval, N-1 timers are required; if a pulse is detected while all of the timers are energized then it is an indication that N pulses have occurred within the test time interval.

United States Patent Inventor George J. Harris [56] References Cited Middlesex, Mass. UNITED STATES PATENTS 95w 3 1 3,289,783 12/1966 Buhler 246/l 82 R x 1 3,284,788 11/1966 Hudson 324 78 ux Patented Dec. 14, 1971 I I Q Assignee American Optical Corporation P y mi r-Alfred E. Smith Southbridge, Mlass. Allorneys-William C. Nealon, Noble S. Williams, Robert J.

Bird and Amster and Rothstein SLIDING INTERVAL EVENT DETECTOR 5 Claims,4 Drawing Figs. ABSTRACT: A system for detecting the occurrence of a 4 7 predetermined number of pulses in a predetermined sliding" US. Cl. 32 8 Q, test time interval. A plurality of timers is provided each having 324/181 a timing interval equal to the test time interval. Each input Int. Cl G0lr 23/02, pulse Sets one ofthe mew To detect N Pulses in the test time 9/00 interval, N-l timers are required; if a pulse is detected while Field of Search 324/78 (3, a" of he timers are energized hen it is an indication that N 70 pulses have occurred within the test time interval.

WPB "1 14 18 1| l5 S l-MINUTE Tl A S l-MINUTE T2 A S l-MINUTE T3 '22 TlMER TlMER TIMER F R a 1 TI R u 2 T2 R 4* 3 T3 8 l-MINUTE T4 ALARM 24 6 TIMER A s CIRCUIT R 8 4 T4 R o Patented Dec. 14, 1971 3,628,142

2 Sheets-Sheet 1 SLIDING INTERVAL EVENT DETECTOR This invention relates to timing systems, and more particularly to a system for detecting the occurrence of a predeter mined as of events within a predetermined time interval.

in many situations it is necessary to detect the occurrence of a predetermined number of events within a predetermined time interval. For example, in electrocardiograhic monitoring it is very important for the attending physician to be made aware of frequently occurring ventricular premature beats (VPBs). A typical standard is the occurrence of such VPBs within a l-minute interval. if at least 5 VPBs occur during any l-minute interval the physician is alerted via an alarm circuit that the patient requires attention.

Typical frequent-VPB. detectors now on the market are relatively crude and medically inadequate. in a typical system, a counter is provided to count the VPBs which occur during a l-minute interval. At the end of every l-minute interval, a reset pulse clears the counter and the counter starts over gain. if the number accumulated in the counter just prior to resetting exceeds a predetermined number (for example, 5) an alarm is sounded. The basic shortcoming of this method is that it fails to recognize the case where a number of VPBs occur prior to resetting during the latter part of the counting interval, and more VPBs occur just after the reset pulse. Although in the time interval of one minute a number of VPBs may have occurred which should have caused an alarm to be generated, the system fails to recognize this condition because of the arbitrary split of the critical minute into parts of two distinct counting intervals.

It is a general object of my invention to provide a system which continuously measures the number of events (e.g., VPBs) occurring in a *sliding" time interval of predetermined length, so that no matter what the temporal distribution of the events the occurrence of a predetermined number of events in any time interval of the predetermined length will be detected.

Briefly, in accordance with the principles of my invention, various timers are set into operation by successive events (VPB s in the illustrative embodiments of the invention). Each timer has a period of 1 minute and, in order to detect the occurrence of 5 VPBs in any l-minute interval, four timers are required. (In general, to detect N events in any arbitrary sliding time interval, N-l timers are required each having a period equal to the period of interest.) Each VPB sets only one timer, one which is not already set. It is apparent that when all four timers are set, the four VPBs which set them must have all occurred within the last minute. if a fifth VPB is detected while all four times are set, it is an indication that five VPBs have occurred within a l-minute interval.

it is apparent that with such an arrangement the l-minute test interval is sliding -it does not matter when the VPBs occur in an absolute time framework. All that counts is that the fifth VPB occur within one minute after the first.

The order in which the four timers are set by the incoming VPBs is not important, as long s each VPB results in the setting of only one of the previously reset timers. The scheme for distributing incoming VPB pulses to the various timers, depending on which timers are already set, can vary from system to system. Two illustrative distribution schemes are disclosed hereinbelow.

Further objects, features and advantages of my invention will become apparent upon consideration of the following detailed description in conjunction with the drawing, in which:

FIG. 1 depicts a first illustrative embodiment of my invention;

FIG. 2 depicts an illustrative circuit 40 which can be used for the timers of the systems depicted in FIGS. 2 and 4;

FIG. 3 depicts a circuit suitable for the delay elements shown in the systems of FIGS. 2 and 4; and

FIG. 4 depicts a second illustrative embodiment of my invention.

Referring to FIG. 1, a positive pulse appears at terminal 22 to indicate the occurrence of the event to be monitored. The

pulse appearing at terminal 22 is designated +VPB in FIG. 1 only because the illustrative embodiments of the invention are particularly suitable for use as frequent-VPB alarm circuits.

To reset the system, switch 26 is closed and the positive potential of source 25 is extended to the reset input of each of timers 10-13, and the reset input of flip-flop 23. The T output of each timer goes low, with the T output going high. Similarly, the 0 output offlip-flop 23 goes high, with the 1 output going low.

The first pulse at terminal 22, connected to the set input of timer 10, sets the timer with the Tll output going high and the TT output going low. For the next minute the timer remains set. Subsequent +VPB pulses applied] to the set input of the timer have no effect on the timer operation. until the timer resets after 1 minute at which time the next positive input pulse sets it once again.

The step potential at the Ti output of timer [0 is extended through delay element 14 to one input of AND-gate B8. The other input to the AND gate is connected to terminal 22. AND-gate 118 does not operate with the appearance of the first pulse at terminal 22. The input pulse has a duration measured in microseconds. The delay of element 14 is l millisecond. Consequently, the output of delay 14 does not go sufficiently high to energize the associated input of gate 18 until after the input pulse extended to the other gate input has terminated.

If timer 10 is still set when the second pulse appears at terminal 22, the pulse is extended through gate 18 to the set input of the second timer. The T2 output of timer 1 goes high, and the high potential is extended through delay element 15 to one input ofAND-gate 19. The second pulse, appearing at the output of gate 18, is also extended directly to the second input of gate 19. HOwever, the pulse at the output of gate 18 has a duration (in microseconds) equal to the duration of the input pulse, and consequently the lower of the two inputs of gate 19 is deenergized before the output of delay element 15 goes high. Consequently, the second pulse sets timer ill but is not extended through gate 19.

Provided that timers l0 and 11 are still set by the time the third pulse is applied at terminal 22, both of gates 18 and 19 are enabled. The input pulse is extended through gate 18 and then through gate 19 to the set input of timer 12. The third timer turns on with the T3 output going high. The high output is extended through delay element 16 to one input of gate 20. The pulse at the output of 'gate 19, although coupled directly to one input of gate 20, is, not extended through the gate because the pulse terminates before the output of delay element 16 is high enough to enable the gate.

Provided that timers 10, H and 12 are all on when the fourth pulse appears at terminal 22, this pulse is extended through gates l8, l9 and 20 to the set input of timer 13. The output of gate 20 is also coupled directly to an input of gate 21, but due to the incorporation of delay element 17 between the T4 output of timer l3 and one of the inputs of gate 21, the fourth input pulse is not extended through gate 21.

Provided all four timers are on when the fifth pulse appears at terminal 22-which can occur only if the first timer has not yet completed its timing interval, i.e., the fifth pulse occurs within 1 minute of the first pulse--the fifth pulse is extended through all of the AND gates to the set input of flip-flop 23. The 1 output of the flip-flop goes high to energize alarm circuit 24 to indicate that 5 VPBs have: occurred within a 1- minute interval.

Suppose. however. that all four timers are on after the fourth input pulse is applied at terminal 22, but that timer l0 turns off (after its l-minute period of operation) before a fifth pulse is received. in such a case, the fifth pulse is not extended through the four AND gates to flip-flop 23 because AND-gate 18 is not enabled by the T1 output of timer 10. instead, the fifth pulse simply sets timer 10. The pulse terminates before delay element 14 enables gate 18. Consequently, with the appearance of the fifth pulse all four timers are on. The sixth pulse, if it occurs within 1 minute of the second pulse, is extended through all four AND gates to set flip-flop 23.

Similarly, suppose that after the fourth pulse is applied at terminal 22 and all four timers have turned on, more than 1 minute elapses after the appearance of the second pulse. In such a case, both timers l and 11 turn off before the fifth pulse is received. The fifth pulse causes timer to turn on, with timer 11 being the only timer which remains off. The sixth pulse is extended through gate 18 to turn on timer 11; all timers are on and the next. pulse, if it occurs before timer 12 has turned off, triggers the alarm circuit. It should be noted that in such a case it is timer 12 which is the first timer to turn off since the last two timers to have been set were timers 10 and 11. If timer 12 does turn off, the next pulse is extended through gates 18 and 19 to turn it on.

It is apparent that the pulse distribution scheme of FIG. 1 is such that the timer which is set upon the occurrence of each input pulse is always the least significant timer which is not already on. In other words, timer 10 is always the one which is set by an input pulse, provided it is not already on. If timer 10 is already on, it is timer 11 which is selected if it is not already on. Timer 12 is selected if and only if it is not already on and timers l0 and 11 are on. Finally, timer 13 is set by an incoming pulse only if the three timers occuring earlier in the chain are already on.

The scheme can be extended to detect any number of pulses occurring in any time interval. The number of timers required is one less than the number of events to be monitored, and the timing interval of each timer is the time interval of interest. The chain of timers depicted in FIG. 1 can be considered to be a series" chain. Each input pulse is extended down a chain of on" timers to turn on the first reset timer encounted.

It should be noted that in general only N-l timers are required to count N events in the selected timer period. An Nth timer is not necessary since the Nth pulse need simply trigger the alarm circuit.

FIG. 2 depicts a circuit 40 which can be used for each ofthe timers 10-13. Cross-coupled NOR-gates 41 and 42 function as a latch. When a positive pulse is applied to the set input of timer 40, it is extended through NOR-g ate 41 and the output of the gate goes low.'Conductor 51 is initially held at ground potential through resistor .50, and input conductor R is similarly deenergized. With the three inputs of NOR-gate 42 all low, the output goes high to energize the second input of Nor-gate 41. Consequently. even after the pulse at the set input of timer 40 terminates, the output of gate 41 is held low as a result of the'high output of gate 42. Similarly, a positive pulse applied to the reset input of the timer causes the output of gate 42 to go low and the output of gate 41 to go high.

Initially. with the output of gate 41 high, a positive potential isextended through resistor 43 to the base of transistor 46. Thev transistor conducts and current flows from source 44, through resistor 45 and the transistor, to ground. The collector of the transistor is held at ground potential and thus capacitor 47 cannot charge.

However, with the application of a pulse to the set input of the timer, the output of gate 41 goes low. At this time transistor 46 turns off and current flows from source 44, through resistor 45 and capacitor 47, to ground. Unijunction transistor 49 remains off until the voltage across capacitor 47 reaches the firing level. When this firing level is reached, the unijunction transistor turns on, and current flows from source 44, through resistor 48, unijunction transistor 49 and resistor 50, to ground. Similarly, capacitor 47 discharges through the unijunction transistor and resistor 50. The positive potential appearing across resistor 50 is extended along conductor 51 to one input of OR gate 42. This pulse causes the output of gate 42 to go low, resulting in the output of NOR-gate 41 going high. Transistor 46 turns on and capacitor 47 remains shorted to ground until the application of another pulse to the set input of the timer.

Following the application of a pulse to the set input of the timer and the turning off of transistor 46, one minute is required before the voltage across capacitor 47 rises to the firing level of the unijunction transistor. While the capacitor is charging and the timer is on, the output of NOR-gate 42 is high. This output is connected to the T output of the timer which is thus high for as long as the timer is on. Since the T output of the timer is connected to the output of NOR-gate 41, the T output of the timer is low as long as the timer is on. The opposite polarities prevail following the resetting of the timer with the application of a positive pulse to the reset input or the completion of the l-minute timing interval when a positive pulse appears on conductor 51.

FIG. 3 depicts a delay unit 55 which can be used for any delay units 14-17 in FIG. 1. The input to the delay (from the T output ofa timer) is conductor 56, and the output of the delay (extended to the input of an AND gate) is conductor 57. The delay unit itself consists of a resistor 58 and a capacitor 59-a conventional RC integrating network. As is known to those skilled in the art, a positive step on conductor 56 does not result in an immediate positive step on conductor 57. Instead, the potential on conductor 57 grows exponentially. If the time constant of the delay unit is approximately 0.5 milliseconds, the potential of conductor 57 is almost negligible after only a few microseconds have elapsed following the application of a step voltage to conductor 56. Thus when the delay element 55 of FIG. 3 is used in FIG. 1, the input to each AND gate connected to the output of a respective delay unit is not energized by the time the input pulse at terminal 22 (which has a duration in the order of microseconds) has terminated.

FIG. 4 depicts a parallel" distribution scheme. The T output of each of timers 70-73 is extended to the input of a respective one of delay elements 74 -77, and the output of each delay element is extended to an input of a respective one of AND-gates 78-81. This is similar to the arrangement of FIG. 1 except that the chain of FIG. 4 is a closed loop. However, the second input to each AND gate in FIG. 1 is connected to the output of a preceding AND gate in the chain. There is no such arrangement in FIG. 4. Instead, the +VPB pulse on terminal 89 is coupled to an input of each of the four AND-gates 78-81, as well as to inputs of AND-gates 82 and 84. It is this connection of the input terminal in parallel to an input of each of the AND gates that gives rise to the characterization of the system of FIG. 4 as a parallel scheme.

All of the timers, as well as flip-flop 85, can be reset by source 87 with the operation of switch 88. With ll of the timers reset, gates 78-81, as well as to inputs of AND-gates 82 and 84. It is this connection of the input terminal in fparallel to an input of each of the AND gates that gives rise to the characterization of the system of FIG. 4 as a parallel" scheme.

All of the timers, as well as flip-flop 85, can be reset by source 87 with the operation of switch 88. With all of the timers reset, gates 78-81 are disabled since one input of each gate is connected through a delay element to the T output of one of the timers. Similarly, gate 84 is disabled because four of its inputs are connected through delay elements to the deenergized outputs of the timers. However, four of the five inputs to gate 82 are connected to the Tl-T4 outputs of the four timers. Consequently, when all four timers are reset, four of the inputs of gate 82 are energized. The fifth input is connected to input terminal 89, and the first input pulse is extended through gate 82, and OR-gate 83, to the set input of timer 70. The timers turns on and energizes one. input of gate 78 through delay element 74. Although the input pulse also appears at the second input of gate 78, the pulse is not extended through the gate because the input pulse terminates before the output of delay element 74 goes high.

The second pulse at terminal 89, provided timer 70 is still on, is extended through gate 78 to turn on timer 71. In a similar manner, the third pulse is extended through gate 79 (without first going through gate 78) to turn on timer 72, and the fourth pulse, provided it occurs while timer 72 is still on, is extended directly through gate 80 to turn on timer 73.

It will be recalled that in the system of FIG. 1 the first reset timer in the chain is set by each input pulse. This is not true in the case of the system of FIG. 4. As long as any one of the four timers is set, one of the inputs of gate 82 is deenergized, and

the input pulse cannot be extended through gate 82 and OR gate 83 to set timer 70. Instead, the timer which is set is always the first reset timer (in the order 70, 711. 72, 73) which follows an on timer. Suppose that timers ll, 2 and 3 are on and that timer i then completes its timing interval before another input pulse occurs. With only timers 2 and 3 on. the next pulse causes timer d to turn on. It is apparent that in a system such as that of FIG. 41, no matter how many timers are utilized, all of the on timers will always be in sequence. In this analysis. timer 1 is considered to follow timer 4. ln a system such as that of FIG. 1, on the other hand, the on timers need not necessarily be in sequence.

it will be noted that the output of delay unit 77 is extended to one input of gate M. A second input of this gate is connected to the W output of timer 70. Thus two of the inputs of gate M are energized whenever the first timer is off and the fourth timer is'on. The third input of gate 81 is connected to terminal 89, and consequently if timer l is off when timer 4 is on, timer l is the next timer to be set with the appearance of an input pulse.

in effect, the four timers in FIG. 4 are arranged in a closed loop. Gate fill serves in the same capacity as gates 7%,79 and 80-if timer ll is the last on timer in the series of on timers, timer ll will be the next one to be set. Gate 82 is provided in order to select an arbitrary one of the timers (70) to be the starting point in the closed loop. With all timers off, the first input pulse is transmitted through AND-gate 82 and ORgate 83 to set timer 70.

It is apparent that all four timers will be on simultaneously if four input pulses appear at terminal 89 within a period of one minute. The Tll-T4l outputs of the four timers are extended to four of the inputs of gate 84. The fifth input of this gate is connected to input terminal 89. lfa fifth pulse is detected within one minute after the detection of the first of the four preceding pulses. flip-flop 85 switches to the 1 state to turn on alarm circuit 86. The enabling of the first four inputs of gate 84 is an indication that 4 pulses have been detected in an interval less than a minute, and the fifth pulse turns the gate on. instead of providing a fifth timer to monitor the fifth pulse, all that is required is a simple AND gate.

Although the invention has been described with reference to particular embodiments it is to be understood that these embodiments are merely illustrative of the application of the principles of the invention. Numerous modifications may be made therein and other arrangements may be devised without departing from the spirit and scope of'the invention.

What is claimed is:

l. A system for detecting the occurrence of a predetermined number of events within a predetermined time interval comprising a plurality of timing means each energizable for said predetermined time interval for representing the occurrence of an event responsive to the initial energization thereof, means for energizing a deenergized one of said timing means responsive to the occurrence of each event, means for representing the simultaneous energizations of all of said timing means, and means for detecting the occurrence of an event while all ofsaid timing means are energized simultaneously.

2. A system for detecting the occurrence of a predetermined number of pulses within a predetermined time interval comprising a plurality of timers arranged in a series chain, each of said timers having a timing period equal to said predetermined time interval and being energizable for said predetermined time interval responsive to the setting thereof by one ofsaid pulses, means for controlling the setting by each of said pulses of only the first deenergized timer in said series chain, and means for representing the simultaneous energizations of all of said timers.

3. A system in accordance with claim 2 further including means for detecting a pulse while all of said timers are energized.

4. A system for detecting the occurrence of a predetermined number of pulses within a predetermined time interval comprisinga plurality of timers arranged in a closed loop, each of said timers having a timing period equal to said predetermined time interval and being energizable for said predetermined time interval responsive to the setting thereof by one of said pulses, means for controlling the setting by each of said pulses of only the first deenergized timer in said closed loop following the last energized timer in a selected direction around said loop, means for controlling the setting by one of said pulses of a preselected one of said timers when all of said timers are deenergized and means for representing the simultaneous energizations of all of said timers.

5. A system in accordance with claim 4 further including means for detecting a pulse while all of said timers are energized. 

1. A system for detecting the occurrence of a predetermined number of events within a predetermined time interval comprising a plurality of timing means each energizable for said predetermined time interval for representing the occurrence of an event responsive to the initial energization thereof, means for energizing a deenergized one of said timing means responsive to the occurrence of each event, (and) means for representing the simultaneous energizations of all of said timing means (.), and means for detecting the occurrence of an event while all of said timing means are energized simultaneously.
 2. A system for detecting the occurrence of a predetermined number of pulses within a predetermined time interval comprising a plurality of timers arranged in a series chain, each of said timers having a timing period equal to said predetermined time interval and being energizable for said predetermined time interval responsive to the setting thereof by one of said pulses, means for controlling the setting by each of said pulses of only the first deenergized timer in said series chain, and means for representing the simultaneous energizations of all said timers.
 3. A system in accordance with claim 2 further including means for detecting a pulse while all of said timers are energized.
 4. A system for detecting the occurrence of a predetermined number of pulses within a predetermined time interval comprising a plurality of timers arranged in a closed loop, each of said timers having a timing period equal to said predetermined time interval and being energizable for said predetermined time interval responsive to the setting thereof by one of said pulses, means for controlling the setting by each of said pulses of only the first deenergized timer in said closed loop following the last energized timer in a selected direction around said loop, means for controlling the setting by one of said pulses of a preselected one of said timers when all of said timers are deenergized, and means for representing the simultaneous energizations of all of said timers.
 5. A system in accordance with claim 4 further including means for detecting a pulse while all of said timers are energized. 